1. Field of the Invention
The present invention is related to an information processing apparatus executing multiple operations concurrently and/or overlapped with static scheduling of the order of operations execution including simultaneous modification of data stored in a multiport register file, if operations are completed in an order different from the one specified in the program.
2. Description of the Prior Art
Pipeline, multi-instruction issue and multi-instruction execution are widely used in the high performance processor design. However, parallel execution in a pipeline of multiple operations on different stages poses a number of problems and requires special measures be taken to save the correct processor condition. One problem is an output dependence or Write After Write (WAW) hazard, which occurs during writing the results of operations with different execution times into a register file.
A WAW hazard occurs when the executive pipeline contains operations with the same write addresses of the results into the register file and different execution time. Under these conditions, it is necessary to ensure the order of writing the results into the register file specified in the program. Actually, such a situation takes place in the programs while switching to a new program branch, which does not take into account the registers use scheduling in the previous branch. Another example is a super optimal scheduling of the operations execution based on the active use of the bypass during the transfer of operations results into the following operations as operands rather than during the transfers through the register file.
One way to resolve the WAW hazard problem is to block the issue of a wide instruction containing the operation bringing about WAW hazard into the executive pipeline, before the execution of the earlier issued operation with the same write address is completed. However, such a solution results in decreasing the processor throughput. In superscalar dynamic architecture use is made of the methods that allow avoiding the throughput losses caused by the WAW hazard.
In the first approach, the architecture registers are dynamically renamed and a new register from the list of free registers is allocated for each new decoded operation. Thus, the conflicts connected with the use of the same write addresses in different operations are avoided.
In the second approach, use of a so-called completion unit ensures writing into the register file in the order of decoding the instructions. In the processor using the completion unit, operations may be executed out of order, but writes into the register file are performed in the issue order.
Both above mentioned approaches require substantial additional hardware and a complex control of the bypass. This complexity is justified for the microprocessors with dynamic scheduling of the instruction issue, but in the microprocessors with static scheduling, the main problems connected with similar conflicts may be resolved in the software, which allows use of more simple hardware ensuring support for the cases when static scheduling appears insufficient.